The present invention relates to an architecture of a memory circuit and particularly to a redundancy circuit technique, which is applied to DRAM of a multi-bit I/O, having an overlaid-DQ bus.
In recent years, various kinds of information devices such as a personal computer, an office computer, etc, are used. Particularly, in the personal computer, it is required that data of motion pictures and voice be processed at high speed. However, as compared with the high speed operation of a central processing unit of information device, the speed-up of the operation of a general memory device has not been advanced yet. In order to solve this problem, various kinds of architectures such as synchronous DRAM, RAMBUS DRAM are used to speed up the operation of the general memory device (particularly, DRAM). However, it is required that a data transfer rate is largely ensured without using such a special architecture.
In the process of the general DRAM of a 16M bit generation, two metal line layers, including a bit selection line and a global data line (DQ line), are generally used.
FIG. 1 is a block diagram showing one example of DRAM of 16M bit generation. In the figure, DRAM is partially extracted from a chip of DRAM. Two memory cells (MA1, MA2) are arranged, and a sense amplifier circuit section (S/A), which comprises a plurality of sense amplifiers, is provided at both sides of S/A. A line to which data is transferred from a bit line BL (BBL) is a DQ (BDQ) line. BBL and BL are signal lines showing a complementary relationship therebetween. BDQ and DQ are signal lines showing a complementary relationship therebetween. Row decoders for selecting a word line WL are provided in a row direction. The following explains a case of accessing to data of memory cell MC selected by WL0 and BL0. At this time, BBL0 is a dummy bit line to which a reference voltage is supplied.
To read data of memory cell MC, a voltage (data of MC) transmitted to BL0 and a voltage (reference voltage) transmitted to BBL0 are supplied to a sense amplifier S/A2 connected to BL0, BBL0. Next, data of the memory cell MC is sensed by S/A2 to be amplified. After amplifying data sufficiently, a column selection line CSL is set to be high level, and a transistor of a transfer gate is turned on. Thereby, data is transferred to DQ1 and BDQ1.
Thus, the conventional structure of DRAM is formed such that the bit line BL and the DQ line are intersected each other to have a predetermined connecting point of the sense amplifier circuit section S/A. To realize the multi-bit I/O by use of the arrangement of the DQ line shown in FIG. 1, data must be read from a large number of pairs of DQ lines so that each S/A connected to each pair of DQ lines is operated. As a result, power consumption of the chip is increases.
In consideration of the above-mentioned problem, there is used a system in which the DQ lines are arranged in a direction parallel to the bit lines BL as an architecture of DRAM having multi-bit I/O, that is, the overlaid-DQ system (overlaid DQ bus architecture).
FIG. 2 is a circuit diagram explaining the system structure of the overlaid-DQ system. The overlaid-DQ system is suitable for a memory device for reading/writing a large amount of data at one time. FIG. 2 shows a case of accessing to data of memory cell MC selected by WL0 and BL0. At this time, BBL0 is a dummy bit line to which a reference voltage is supplied.
To read data of the memory cell MC, the voltage (data of MC) transmitted to BL0 and the voltage (reference voltage) transmitted to BBL0 are supplied to the sense amplifier S/A2 connected to BL0, BBL0. Next, data of the memory cell MC is sensed by S/A2 to be amplified. After amplifying data sufficiently, the transfer gate is set to be a conductive state by a column switch signal CSW2. Thereby, data is transferred to DQ1 and BDQ1.
For example, regarding the memory cell selected by WL0, in the sense amplifier circuit section S/A belonging to the memory cell array MA1, only sense amplifiers in S/A2 or S/A1 are operated, and CSW2 (or CSW1) is set to be in an active level. Thereby, data of each memory cell can be read to the large number of pairs of DQ lines (DQ0, BDQ0 to DQn, BDQn).
In other words, the sense amplifiers in S/A1 are operated and CSW1 is set to be in the active level. Then, among the memory cells selected by the arbitrary word line WL in the memory cell array MA1, data of each memory cell connected to bit lines of even number such as BL1, BBL1 is read to each pair of DQ lines.
Also, the sense amplifiers in S/A2 are operated and CSW2 is set to be in the active level. Then, among the memory cells selected by the arbitrary word line WL in the memory cell array MA1, data of each memory cell connected to bit lines of odd number such as BL0, BBL0 is read to each pair of DQ lines.
Moreover, the sense amplifiers in S/A3 are operated and CSW3 is set to be in the active level. Then, among the memory cells selected by the arbitrary word line WL in the memory cell array MA2, data of each memory cell connected to bit lines of odd number such as BL2, BBL2 is read to each pair of DQ lines.
Also, the sense amplifiers in S/A4 are operated and CSW4 is set to be in the active level. Then, among the memory cells selected by the arbitrary word line WL in the memory cell array MA2, data of each memory cell connected to bit lines of even number such as BL3, BBL3 is read to each pair of DQ lines.
As compared with the structure of the multi-bit I/O shown in FIG. 1, the structure shown in FIG. 2 can restrain an increase in consumption power. Also, in the overlaid-DQ system, a large number of DQ lines are arranged in a form that they are overlaid above the cell array. As a result, there can be realized the structure in which the size of the chip is not increased.
However, even in the memory device using the above-explained overlaid-DQ system, variations of the process occur in the DQ lines, the sense amplifiers, and the memory cells. Therefore, it can be considered that possibility that the memory cell will be defective is the same as the case of the general DRAM. However, the redundancy technique for replacing the defective cell with a redundancy cell has not been optimized yet.